Title :
A simple output impedance model for Doherty peaking sub-amplifiers biased in Class C
Author_Institution :
Freescale Semicond. Inc., Tempe, AZ, USA
Abstract :
A simple model of the Doherty peaking sub-amplifier is proposed that approximates the frequency-dependant behavior of its output impedance as seen at the reference plane of the carrier-peaking combining node. The analytical model is useful in that it shows the degradation of the output impedance over frequency as a function of fundamental device and network properties: device output capacitance, transformation ratio, and network delay. The model provides significant insight into the behavior and theoretical upper limit of output impedance when the sub-amplifier is disengaged and provides a benchmark for which to compare practical results for broadband Doherty amplifier designs. By augmenting the model with subthreshold drain-to-source resistance, excellent agreement is shown between the model and experimental results over frequency.
Keywords :
capacitance; electric resistance; power amplifiers; wideband amplifiers; Doherty peaking subamplifier; broadband Doherty amplifier design; carrier-peaking combining node; class C amplifier; device output capacitance; frequency-dependant behavior; network delay; network properties; output impedance model; power amplifier; subthreshold drain-to-source resistance; transformation ratio; Capacitance; Delays; Impedance; Impedance matching; Integrated circuit modeling; Load modeling; Numerical models; Class C; Doherty amplifier; broadband; off-state; output impedance; power amplifier;
Conference_Titel :
Power Amplifiers for Wireless and Radio Applications (PAWR), 2013 IEEE Topical Conference on
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4673-2915-6
Electronic_ISBN :
978-1-4673-2931-6
DOI :
10.1109/PAWR.2013.6490192