Title :
Test vector compression using EDA-ATE synergies
Author :
Khoche, Ajay ; Volkerink, Erik ; Rivoir, Jochen ; Mitra, Subhasish
Author_Institution :
Agilent Technol. Inc., Palo Alto, CA, USA
Abstract :
This paper presents a new test vector compression technique, which utilizes synergies between Automatic Test Pattern Generation (ATPG) tools provided by EDA (Electronic Design Automation) vendors and Automatic Test Equipment (ATE). The basic approach is to achieve significant compression by agreeing between ATE and ATPG on how to fill don´t care values in the test vectors such that these bits need not be stored on ATE and also possibly not communicated to DUT if decompression is done on chip. Our new technique allows sub-vector level fine grained mixing of pseudo-randomly generated bits and ATPG generated bits. Experimental results, on an actual industrial network processor design, show a compression ratio of about 17x.
Keywords :
automatic test equipment; automatic test pattern generation; data compression; integrated circuit testing; ATE; ATPG generated bits; ATPG tools; EDA vendors; automatic test equipment; automatic test pattern generation tools; electronic design automation vendors; onchip decompression; pseudo-randomly generated bits; sub-vector level fine grained mixing; test vector compression technique; test vectors; Automatic test equipment; Automatic test pattern generation; Automatic testing; Bandwidth; Built-in self-test; Electronic design automation and methodology; Electronic equipment testing; Process design; Test data compression; Vectors;
Conference_Titel :
VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE
Print_ISBN :
0-7695-1570-3
DOI :
10.1109/VTS.2002.1011118