On-chip network resource management design and validation

Designing interconnection networks for systems on-a-chip is getting more complex due to the increasing number and heterogeneity of elements they connect, the variety of technologies adopted to transmit and route information, the performance and cost requirements and constraints they have to satisfy. The complexity of such transmission fabrics gets then closer to that of telecommunication networks. Designers face more and more often the possibility of importing techniques from the classical world of communication networks, and to augment interconnection fabrics with reconfigurable features and dynamic resource management. In order to evaluate such opportunities, they have to be able to simulate the architectures in mind under the most realistic possible conditions. Up to now, the only tools exploited for the simulation of such complex networks have been network simulators. In this paper we consider the possibility of using MPSoC simulation frameworks for the early evaluation of reconfigurable networks-on-chip (NoCs), with the advantage of providing more realistic scenarios and stimuli to the network, and with the aim of obtaining more reliable evaluations.