DocumentCode
1820792
Title
VERIFUL: VERIfication using FUnctional Learning
Author
Mukherjee, Rajarshi ; Jain, Jawahar ; Fujita, Masahiro
Author_Institution
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
fYear
1995
fDate
6-9 Mar 1995
Firstpage
444
Lastpage
448
Abstract
It is well known that learning (i.e., indirect implications) based techniques perform very well in many instances of combinational circuit verification when the two circuits being verified have many corresponding internal equivalent points. We present some results on combinational circuit design verification using a powerful, and highly general learning technique called functional learning. Functional learning is based on OBDDs and hence can efficiently learn novel implications based on functional manipulation
Keywords
Boolean functions; combinational circuits; learning systems; logic CAD; logic design; OBDD; VERIFUL; combinational circuit design; combinational circuit verification; functional learning; functional manipulation; learning technique; ordered binary decision diagrams; Automatic test pattern generation; Boolean functions; Circuit synthesis; Combinational circuits; Design automation; Digital circuits; Industrial relations; Logic circuits; Logic design; Observability;
fLanguage
English
Publisher
ieee
Conference_Titel
European Design and Test Conference, 1995. ED&TC 1995, Proceedings.
Conference_Location
Paris
Print_ISBN
0-8186-7039-8
Type
conf
DOI
10.1109/EDTC.1995.470358
Filename
470358
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