Design and implementation of dynamic key based stream cipher for cryptographic processor

In this paper, a new design for dynamic key based stream cipher is proposed for the hardware cryptographic applications such as data transmission and information security. Unlike the static key based existing stream ciphers, the novelty of this proposed stream cipher is based on dynamic key, generated by Toeplitz hash function which is used as a key for RC4 stream cipher. Further, this key is used to generate the dynamic hardware key for the cryptographic processor. The proposed design is implemented on targeting a commercially available xilinx spartan 3E xc3s500e-4fg320 FPGA device. This implementation of the proposed methodology accomplishes data throughput of 520 Mbps with the initial latency of 17 clock cycles, at a maximum clock frequency of 65 MHz with the total estimated power consumption of 131 mW. The excellence of the generated random hardware key values of our proposed method is validated using NIST statistical test suites. The proposed design in this paper is considerably improved in terms of frequency, throughput performance and area consumed compared to existing design.