DocumentCode
1820902
Title
On using efficient test sequences for BIST
Author
David, R. ; Girard, P. ; Landrault, C. ; Pravossoudovitch, S. ; Virazel, A.
Author_Institution
Lab. d´´Automatique de Grenoble, St. Martin d´´Heres, France
fYear
2002
fDate
2002
Firstpage
145
Lastpage
150
Abstract
High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Input Change (RSIC) generation, that can be used to generate tests for many arbitrary misbehaviors that can occur in digital systems, thus providing a single on-chip test generation solution.
Keywords
built-in self test; integrated circuit testing; logic testing; sequences; BIST; digital systems; efficient test sequences; high defect coverage; logic BIST; on-chip test generation solution; random sequences; random single input change generation; submicron IC process technology; test vector generation technique; Built-in self-test; Circuit testing; Costs; Digital systems; Logic testing; Performance evaluation; Semiconductor device modeling; System testing; System-on-a-chip; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE
Print_ISBN
0-7695-1570-3
Type
conf
DOI
10.1109/VTS.2002.1011126
Filename
1011126
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