Test vector modification for power reduction during scan testing

Author

Kajihara, Seiji ; Ishida, Koji ; Miyase, Kohei

Author_Institution

Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Japan

fYear

2002

fDate

2002

Firstpage

160

Lastpage

165

Abstract

This paper presents a test vector modification method for reducing power dissipation during test application for a full-scan circuit. The method first identifies a set of don´t care (X) inputs of given test vectors, to which either logic value 0 or 1 can be assigned without losing fault coverage. Then, the method reassigns logic values to the X inputs so as to decrease switching activity of the circuit during scan shifting. Experimental results for benchmark circuits show the proposed method could decrease switching activity of a given test set to 48% of the original test set.

Keywords

CMOS logic circuits; automatic test pattern generation; boundary scan testing; integrated circuit testing; logic testing; low-power electronics; sequential circuits; ATPG; CMOS digital circuit; benchmark circuits; don´t care inputs; fault coverage; full-scan circuit; full-scan sequential circuits; logic value reassignment; power dissipation reduction; pseudo-primary output; scan shifting; scan testing; stuck-at faults; switching activity; test vector modification; Benchmark testing; CMOS logic circuits; Circuit faults; Circuit testing; Electronic equipment testing; Flip-flops; Logic testing; Power dissipation; Switching circuits; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE

Print_ISBN

0-7695-1570-3

Type

conf

DOI

10.1109/VTS.2002.1011128

Filename

1011128