DocumentCode
1821186
Title
Architectural exploration for datapaths with memory hierarchy
Author
Holmes, Nancy D. ; Gajski, Daniel D.
Author_Institution
Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
fYear
1995
fDate
6-9 Mar 1995
Firstpage
340
Lastpage
344
Abstract
In this paper, we present a new design-space exploration algorithm, the architecture explorer (AE), for analyzing performance/cost tradeoffs in memory-intensive applications. AE evaluates FU, bus, and memory cost for a series of performance constraints to produce a performance/cost tradeoff curve. Unlike previous approaches, AE handles both hierarchical and non-hierarchical memory architectures with various speeds of memory
Keywords
hardware description languages; high level synthesis; memory architecture; architectural exploration; architecture explorer; datapaths; design automation; design-space exploration algorithm; functional units; high level synthesis; memory architectures; memory cost; memory hierarchy; memory-intensive applications; performance constraints; performance/cost tradeoffs; Algorithm design and analysis; Computer architecture; Computer science; Costs; Delay estimation; High level synthesis; Information analysis; Performance analysis; Registers; Space exploration;
fLanguage
English
Publisher
ieee
Conference_Titel
European Design and Test Conference, 1995. ED&TC 1995, Proceedings.
Conference_Location
Paris
Print_ISBN
0-8186-7039-8
Type
conf
DOI
10.1109/EDTC.1995.470374
Filename
470374
Link To Document