Title :
A CMOS signal conditioning ASIC for large silicon pixels
Author :
Walter, J. ; Britton, C. ; Fairstein, E. ; Garber, F.W. ; Simpson, M.
Author_Institution :
IntraSpec Inc., Oak Ridge, TN, USA
Abstract :
We designed, constructed and tested a CMOS ASIC consisting of a preamplifier, shaping amplifier, and externally adjustable discriminator. This device designed for detectors with reasonably fast rise times (compared to 1 μs) and capacitances in the range of 5 to 100 pF. The design was implemented with both PMOS and NMOS inputs. The NMOS version has a superior noise slope of 7 RMS e/pF and an average noise at 6 pF input load of less than 375 RMS electrons. The charge conversion sensitivity is 2.4 V/pC and the power drain is less than 10 mW/channel
Keywords :
CMOS analogue integrated circuits; application specific integrated circuits; detector circuits; discriminators; nuclear electronics; position sensitive particle detectors; preamplifiers; pulse amplifiers; pulse shaping circuits; signal processing; silicon radiation detectors; 5 to 100 pF; CMOS signal conditioning ASIC; NMOS input; PMOS input; Si; average noise; charge conversion sensitivity; externally adjustable discriminator; large Si pixels; noise slope; particle detectors; power drain; preamplifier; shaping amplifier; Application specific integrated circuits; Capacitance; Costs; Detectors; MOS devices; Noise shaping; Preamplifiers; Silicon; Switches; Testing;
Conference_Titel :
Nuclear Science Symposium, 1996. Conference Record., 1996 IEEE
Conference_Location :
Anaheim, CA
Print_ISBN :
0-7803-3534-1
DOI :
10.1109/NSSMIC.1996.591045
