DocumentCode :
1821343
Title :
A testability measure for hierarchical design environments
Author :
Lee, Mike H C ; Tao, D.L.
Author_Institution :
Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA
fYear :
1995
fDate :
6-9 Mar 1995
Firstpage :
303
Lastpage :
307
Abstract :
In this paper a new approach is proposed to compute testability of a combinational circuit in a hierarchical design environment. The testability of a circuit is first computed at the functional level using the Walsh expression of the functional block, and its complexity is linear with respect to the number of functional blocks. The functional level testability measure is then used to compute the testability at the gate/switch level. Our extensive simulation results show that the testability measure of the proposed method reflects closely to the actual testability measure (both at the functional level and the gate level) when the granularity of a functional block is much higher than that of primitive gates
Keywords :
Walsh functions; circuit CAD; combinational circuits; design for testability; logic CAD; logic testing; Walsh expression; combinational circuit; functional level; gate/switch level; hierarchical design environments; simulation; testability measure; Automatic testing; Circuit simulation; Circuit testing; Combinational circuits; Equations; Logic functions; Logic testing; Size measurement; Switches; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
European Design and Test Conference, 1995. ED&TC 1995, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-7039-8
Type :
conf
DOI :
10.1109/EDTC.1995.470380
Filename :
470380
Link To Document :
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