Title :
Design for testability and testing of IEEE 1149.1 TAP controller
Author :
Mitra, Subhasish ; McCluskey, Edward J. ; Makar, Samy
Author_Institution :
Intel Corp., Sacramento, CA, USA
Abstract :
The Test Access Port (TAP) controller is a very important circuit present in all IC chips that are compliant with the IEEE 1149.1 Boundary Scan standard. Although the main purpose of boundary scan is to facilitate board-level testing, it is also used for many other testing and non-testing purposes (e.g., memory and logic BIST wrappers to enable embedded core test, programming FPGAs, checkpointing and recovery of dependable systems, etc.). Hence, it is important to thoroughly test the TAP controller before using it for other purposes. In this paper, we present techniques for designing and testing the TAP controller. Our design techniques simplify the procedure to test the TAP controller by orders of magnitude compared to previously published results. Our TAP controller design technique does not require any extra I/O pins and can be easily automated and incorporated into test tools.
Keywords :
IEEE standards; boundary scan testing; built-in self test; design for testability; field programmable gate arrays; integrated circuit testing; logic testing; peripheral interfaces; FPGA programming; IEEE 1149.1 TAP controller; IEEE 1149.1 boundary scan standard; board-level testing; checkpointing; concurrent error detection; dependable system recovery; design for testability; design techniques; embedded core test; logic BIST; memory BIST; test access port controller; totally self-checking comparator designs; Automatic control; Built-in self-test; Checkpointing; Circuit testing; Design for testability; Field programmable gate arrays; Integrated circuit testing; Logic programming; Logic testing; System testing;
Conference_Titel :
VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE
Print_ISBN :
0-7695-1570-3
DOI :
10.1109/VTS.2002.1011145
