DocumentCode
1821457
Title
GARDA: a diagnostic ATPG for large synchronous sequential circuits
Author
Corno, F. ; Prinetto, P. ; Rebaudengo, M. ; Reorda, M. Sonza
Author_Institution
Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
fYear
1995
fDate
6-9 Mar 1995
Firstpage
267
Lastpage
271
Abstract
The paper deals with automated generation of diagnostic test sequences for synchronous sequential circuits. An algorithm is proposed, named GARDA, which is suitable to produce good results with acceptable CPU time and memory requirements even for the largest benchmark circuits. The algorithm is based on Genetic Algorithms, and experimental results are provided which demonstrate the effectiveness of the approach
Keywords
VLSI; automatic testing; fault diagnosis; genetic algorithms; integrated circuit testing; logic testing; sequential circuits; CPU time; GARDA; benchmark circuits; diagnostic ATPG; diagnostic test sequences; genetic algorithms; memory requirements; synchronous sequential circuits; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Fault diagnosis; Genetic algorithms; Partitioning algorithms; Sequential analysis; Sequential circuits; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
European Design and Test Conference, 1995. ED&TC 1995, Proceedings.
Conference_Location
Paris
Print_ISBN
0-8186-7039-8
Type
conf
DOI
10.1109/EDTC.1995.470385
Filename
470385
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