DocumentCode :
1821542
Title :
Exploiting dominance and equivalence using fault tuples
Author :
Dwarakanath, KumarN ; Blanton, R.D.
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
fYear :
2002
fDate :
2002
Firstpage :
269
Lastpage :
274
Abstract :
Local dominance and equivalence relationships for a single fault type have been exploited to reduce test set size and test generation time. However, these relationships have not been explored for multiple fault types. Using fault tuples, we describe how local dominance and equivalence relationships across various fault types can be derived. We also describe how the derived relationships can be used to order the faults efficiently for test generation in order to reduce test set size. Initial results using our ordered fault lists for ISCAS85 and ITC99 benchmark circuits reveals that test set size can be reduced by as much as 19%.
Keywords :
automatic test pattern generation; fault simulation; integrated circuit testing; logic testing; ATPG; ISCAS85 benchmark circuits; ITC99 benchmark circuits; equivalence relationships; fault simulation tool; fault tuples; local dominance relationships; multiple fault types; single stuck line faults; test generation time; test set size; transistor stuck-open faults; transition faults; Benchmark testing; Circuit faults; Circuit simulation; Circuit testing; Electronic mail; Logic testing; Performance evaluation; Silicon; System testing; Virtual prototyping;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE
Print_ISBN :
0-7695-1570-3
Type :
conf
DOI :
10.1109/VTS.2002.1011151
Filename :
1011151
Link To Document :
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