FPGA realisation of multiplierless FIR filter architectures

In this paper, FPGA realization of MUX based multiplier and odd multiple scheme architectures are proposed for FIR filter and discussed in terms of complexity. In digital filter implementation, the multiplier usage is avoided by using MUX based multiplier and Look Up Table (LUT) based multiplier. These multipliers are used for constructing direct form FIR filters with signed number representation. The two architectures have been implemented using Verilog and synthesized using Altera Cyclone II EP2C35F672C6. The performance is analyzed for 4,8,16 tap filters. The results show that for a MUX based multiplier architecture occupies ¼th area compared with Odd multiple scheme LUT based filters.