Title :
Test pattern generation for signal integrity faults on long interconnects
Author :
Attarha, Amir ; Nourani, Mehrdad
Author_Institution :
Adv. DSP Dev., LSI Logic Corp., Plano, TX, USA
Abstract :
In this paper we present a test pattern generation algorithm aiming at signal integrity faults on long interconnects. This is achieved by considering the effect of inputs and parasitic RLC elements of the interconnect. To enhance the performance of test generation process, model order reduction methodology is employed. This strategy significantly improves the simulation time with slight loss of accuracy.
Keywords :
VLSI; automatic test pattern generation; fault simulation; integrated circuit interconnections; integrated circuit testing; reduced order systems; VLSI technology; integrity fault model; long interconnects; model order reduction methodology; parasitic RLC elements; signal integrity; signal integrity faults; simulation time; test pattern generation algorithm; Circuit faults; Circuit simulation; Circuit testing; Crosstalk; Delay effects; Fault detection; Integrated circuit interconnections; Poles and zeros; RLC circuits; Test pattern generators;
Conference_Titel :
VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE
Print_ISBN :
0-7695-1570-3
DOI :
10.1109/VTS.2002.1011162
