Title :
Proceedings the European Design and Test Conference. ED&TC 1995
Abstract :
The following topics were dealt with: DSP and multimedia; mixed-signal DFT; architectural timing optimization; circuit partitioning; combinational logic synthesis; analogue and mixed signal ICs; memory testing; sequential logic synthesis; high speed telecom design; system synthesis; advanced DFT techniques; digital and system simulation; code generation; sequential ATPG and diagnosis; CAD frameworks; test generation and testability; symbolic traversal techniques; architectural synthesis; self-checking; design methodologies; power and delay issues; BIST; logic representation and verification; mixed-signal test; hierarchical layout; ASIP modeling and design; delay testing and diagnosis; analogue simulation algorithms; pipeline processor design; IDDQ testing
Keywords :
analogue integrated circuits; analogue processing circuits; analogue simulation; application specific integrated circuits; automatic testing; built-in self test; circuit CAD; circuit layout CAD; combinational circuits; delays; design for testability; digital simulation; fault diagnosis; integrated circuit design; integrated circuit layout; integrated circuit testing; integrated memory circuits; logic CAD; logic design; logic partitioning; logic testing; mixed analogue-digital integrated circuits; sequential circuits; timing; ASIP design; DSP; analogue ICs; digital simulation; logic verification; mixed-signal DFT; multimedia; sequential diagnosis;
Conference_Titel :
European Design and Test Conference, 1995. ED&TC 1995, Proceedings.
Conference_Location :
Paris, France
Print_ISBN :
0-8186-7039-8
DOI :
10.1109/EDTC.1995.470396
