Title :
Improved test monitor circuit in power pin DfT
Author :
Schuttert, Rodger ; De Jong, Frans ; Kup, Ben
Author_Institution :
Philips Res., Netherlands
Abstract :
The power pin monitor cell developed by Philips was a significant step in solving the problem of detecting open power pins in paralleled power pin IC designs. This paper present an improved monitor cell design that provides better detection and it is further enhanced by the addition of an improved boundary scan control mechanism. Extensive trials confirm the cell performance and the presented results are analysed and discussed The cells were observed and controlled using an IEEE Std 1149.1 TAP controller.
Keywords :
CMOS integrated circuits; boundary scan testing; design for testability; fault diagnosis; integrated circuit testing; CMOS process; IEEE 1149.1 TAP controller; Philips; boundary scan control mechanism; cell performance; open power pin detection; paralleled power pin IC designs; power pin design for test; power pin monitor cell; test monitor circuit; Circuit testing; Decision support systems; Fiber reinforced plastics; Monitoring; Very large scale integration; Virtual reality;
Conference_Titel :
VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE
Print_ISBN :
0-7695-1570-3
DOI :
10.1109/VTS.2002.1011163
