The SOBER Family Ciphers Reconfigurable Processing Architecture Design

The SOBER family ciphers are widely used in embedded devices. For improving these cipherspsila processing speed, this paper introduces the reconfigurable processing architecture design for them. According to need, the reconfigurable processing architecture can implement SOBER, SOBER-II,S16,S32,SOBER t-class and SOBER-128 stream ciphers. The prototype of the reconfigurable processing architecture has been implemented in Alterapsilas EP2S60F1020C5 FPGA. It is proved by experiment that it uses fewer hardware resources and itpsilas process speed can achieve W*100M bits/s(W is the data width of the ciphers).