Title :
Post-layout optimization of power and timing for ECL LSIs
Author :
Onozawa, Akira ; Kitazawa, Hitoshi ; Kawai, Kenji
Author_Institution :
NTT LSI Labs., Atsugi, Japan
Abstract :
An optimization algorithm for power and timing of bipolar ECL LSls is proposed. The power dissipation is minimized by a nonlinear programming solver under accurate timing constraints extracted from layout. The power and delay time of an ECL gate are considered functions of its switching current which is regulated by programming its resistors. Experimental results show significant power reductions for circuits including a real chip without degrading the performance
Keywords :
bipolar logic circuits; circuit CAD; circuit optimisation; emitter-coupled logic; integrated circuit design; integrated circuit modelling; large scale integration; logic CAD; nonlinear programming; timing; ECL LSIs; bipolar ECL LSl; delay time; nonlinear programming solver; optimization algorithm; post-layout optimization; power dissipation; switching current; timing; CMOS technology; Circuits; Clocks; Constraint optimization; Delay; Large scale integration; Power dissipation; Resistors; Synchronous digital hierarchy; Timing;
Conference_Titel :
European Design and Test Conference, 1995. ED&TC 1995, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-7039-8
DOI :
10.1109/EDTC.1995.470402
