Backlog Bounds Analysis of Different On-chip Cache Coherence Policies: A Network Calculus-Based Approch

To analyze and compare buffer size requirements of different cache coherence policies will provide beneficial guidelines for NoC design. However, it is not an easy task, because 1)packet flows generated by cache coherence events do not conform to the Poisson process, traditional queue theorem can´t be applied to the performance analyzing for the NoCs that support cache coherence, 2) broadcast or multicast operations, which will duplicate the cache coherence packets, makes the analysis much more complicated. To address these challenges, in this paper, we use the stochastic network calculus to analyze the backlog bounds of different cache coherence policies. Specifically, we utilize Markov-modulated On-Off (MMOO) flow to model the arrival process of cache coherence events, and then deduce the general backlog bounds for different cache coherence policies. Furthermore, to deal with packet duplication issues in broadcast or multicast operations, we develop an analytical model based on scaling functions to study their impacts on backlog bounds.