Title :
A 370-MHz memory built-in self-test state machine
Author :
Adams, R. Dean ; Connor, John ; Koch, Garrett S. ; Ternullo, Luigi, Jr.
Author_Institution :
Microelectron. Div., IBM Corp., Essex Junction, VT, USA
Abstract :
Hardware and simulation results for a 370 MHz memory built-in self-test state machine are presented. Dynamic differential cascode voltage switch logic, unique clocking techniques, and logic pipelining were used to achieve the 370 MHz performance. Testing of multiple SRAMs and content addressable memories is accomplished with deterministic patterns generated by the state machine. Inclusion of a programmable pattern implemented via scan initialization provides test-pattern flexibility. Failing addresses are stored for redundancy implementation
Keywords :
CMOS logic circuits; SRAM chips; built-in self test; content-addressable storage; integrated circuit testing; integrated memory circuits; logic testing; redundancy; 370 MHz; DCVS logic; built-in self-test; clocking techniques; content addressable memories; deterministic patterns; dynamic differential cascode voltage switch logic; failing addresses storage; logic pipelining; memory BIST state machine; multiple SRAMs; programmable pattern; redundancy implementation; scan initialization; test-pattern flexibility; Associative memory; Built-in self-test; Clocks; Hardware; Logic; Pipeline processing; Switches; Test pattern generators; Testing; Voltage;
Conference_Titel :
European Design and Test Conference, 1995. ED&TC 1995, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-7039-8
DOI :
10.1109/EDTC.1995.470407
