DocumentCode :
1822502
Title :
Exact scheduling strategies based on bipartite graph matching
Author :
Timmer, Adwin H. ; Jess, Jochen A G
Author_Institution :
Design Autom. Sect., Eindhoven Univ. of Technol., Netherlands
fYear :
1995
fDate :
6-9 Mar 1995
Firstpage :
42
Lastpage :
47
Abstract :
Scheduling is one of the central tasks in high-level synthesis. In recent publications a bipartite graph matching formulation has been introduced to prune the search space of schedulers. In this paper, we improve that formulation and introduce two novel aspects related to the way the search space is traversed, namely problem formulation and bottleneck identification. The approach results in a very run time efficient branch-and-bound scheduler searching for a correct ordering of operations from which a schedule can be derived in linear time. The results show that the use of these bipartite graph matching strategies leads to the most run time efficient exact scheduler to date
Keywords :
VLSI; data flow graphs; high level synthesis; scheduling; VLSI; bipartite graph matching; bottleneck identification; branch-and-bound scheduler; exact scheduling strategies; high-level synthesis; linear time; problem formulation; run time efficient exact scheduler; search space; Arithmetic; Bipartite graph; Circuits; Clocks; Design automation; High level synthesis; Registers; Space technology; Time factors; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
European Design and Test Conference, 1995. ED&TC 1995, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-7039-8
Type :
conf
DOI :
10.1109/EDTC.1995.470422
Filename :
470422
Link To Document :
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