DocumentCode :
1822692
Title :
Density-based hardware-oriented classification for spike sorting microsystems
Author :
Li-Fang Cheng ; Tung-Chien Chen ; Nai-Fu Chang ; Liang-Gee Chen
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear :
2011
fDate :
April 27 2011-May 1 2011
Firstpage :
170
Lastpage :
173
Abstract :
Successful proof-of-concept laboratory experiments on cortically-controlled brain computer interface motivate continued development for neural prosthetic microsystems (NPMs). One of the research directions is to realize realtime spike sorting processors (SSPs) on the NPM. The SSP detects the spikes, extracts the features, and then performs the classification algorithm in realtime in order to differentiate the spikes for the different firing neurons. Several architectures have been designed for the spike detection and feature extraction. However, the classification hardware is missing. To complete the SSP, a density-based hardware-oriented classification algorithm is proposed for hardware implementation. The traditional classification algorithms require a considerable memory space to store all the training features during the processing iteration, which results in a considerable power and area for the hardware. The proposed one is designed based on the density map of the spike features. The density map can be accumulated on-line with the coming of the spike features. Therefore the algorithm can save significant memory space, and is good for efficient hardware implementation.
Keywords :
brain-computer interfaces; feature extraction; medical signal detection; medical signal processing; neurophysiology; prosthetics; signal classification; classification algorithm; cortically-controlled brain computer interface; density-based hardware-oriented classification; feature extraction; firing neurons; hardware-oriented classification; neural prosthetic microsystems; spike sorting microsystems; spike sorting processors; Algorithm design and analysis; Clustering algorithms; Feature extraction; Hardware; Memory management; Sorting; Training;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Neural Engineering (NER), 2011 5th International IEEE/EMBS Conference on
Conference_Location :
Cancun
ISSN :
1948-3546
Print_ISBN :
978-1-4244-4140-2
Type :
conf
DOI :
10.1109/NER.2011.5910515
Filename :
5910515
Link To Document :
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