The impact of thermal imaging procedures on bare die leading toward chip layout design or wafer processing modifications

Instituting dimensional reductions in the layout of CMOS semiconductor chips can lead to unwanted conduction paths significant enough to impact the performance and reliability of the subsequent fabricated integrated circuit. Positive location and identification of the suspect areas is required for the determination of root cause and to enable corrective action to eliminate or minimize the unwanted conduction paths. Empirical methods have to be employed to identify suspect areas since EDA vendors do not have CAD tools sufficiently capable of identifying the suspect areas during the design phase of a complicated high performance integrated circuit. Applying varied thermal imaging procedures and analytical techniques on specially assembled bare chips with defined limited performance identified problematic chip substrate regions and subsequent current conduction through the substrate as the problem in those regions. Corrective chip design layout and assembly techniques were instituted to achieve the required isolation. Although corrective action was achieved through chip design layout modifications, an outline of the wafer processing technology employed will be presented to designate the questionable areas with possible fabrication alterations to avoid the conduction paths encountered