Hardware implementation of montgomery modular multiplication algorithm using iterative architecture

Modular multiplication is an integral part of RSA cryptosystems and its performance heavily determines the performance of the encryption hardware. This paper provides a hardware implementation of Montgomery´s modular multiplication algorithm using iterative architecture. The propsed design is implemented in Verilog HDL and simulated functionally using ModelSim Altera 10.1E. The synthesis is performed using Altera Quartus II 9.1 with target FPGA board Altera DE2-70. The proposed design consumes 17540 logic elements with 15480 LUT and takes 2048 clock cycles to perform multiplication process. Based on trade-off parameter AT² measure, the proposed design offers the best performance among other designs.