DocumentCode
1823754
Title
Crossing-free many-to-one boundary labeling with hyperleaders
Author
Lin, Chun-Cheng
Author_Institution
Dept. of Comput. Sci. & Inf. Eng., Nat. Kaohsiung Univ. of Appl. Sci., Kaohsiung, Taiwan
fYear
2010
fDate
2-5 March 2010
Firstpage
185
Lastpage
192
Abstract
In boundary labeling, each point site is uniquely connected to a label placed on the boundary of an enclosing rectangle by a leader, which may be a rectilinear or straight line segment. Most of the results reported in the literature for boundary labeling deal with the so-called one-to-one boundary labeling, i.e., different sites are labelled differently. In certain applications of boundary labeling, however, more than one site may be required to be connected to a common label. In this case, the presence of crossings among leaders often becomes inevitable such that the labeling often has a high degree of confusion in visualization. In this paper, for multi-site-to-one-label boundary labeling, crossings among leaders are avoided by substituting hyperleaders for leaders and by applying dummy labels (i.e., copies/duplicates of labels). Minimizing the number of dummy labels becomes a critical design issue as dummy labels are not required in the initial setting. Therefore, we consider the problem of minimizing the number of dummy labels for multi-site-to-one-label boundary labeling, i.e., finding the placements of labels and hyperleaders such that the total number of dummy labels is minimized and there are no crossings among hyperleaders. Furthermore, after the number of dummy labels is determined, minimizing the total hyperleader length as well as the bends of hyperleaders is also concerned in postprocessing procedure. In this paper, we present polynomial time algorithms for the above one-side and two-side labeling schemes, and show their correctness from a theoretical point of view. In addition, we provide a simulated annealing algorithm for the four-side labeling schemes with objective to minimize the total number of dummy labels as well as the total leader length. Experimental results show that our four-side solutions look promising, as compared to the optimal solutions.
Keywords
computational complexity; computational geometry; data visualisation; simulated annealing; crossing-free many-to-one boundary labeling; four-side labeling scheme; hyperleader; multisite-to-one-label boundary labeling; polynomial time algorithm; simulated annealing; Batteries; Computer science; Connectors; Labeling; Local area networks; Polynomials; Power supplies; Simulated annealing; Universal Serial Bus; Visualization; Automatic label placement; boundary labeling; information visualization; map labeling;
fLanguage
English
Publisher
ieee
Conference_Titel
Visualization Symposium (PacificVis), 2010 IEEE Pacific
Conference_Location
Taipei
Print_ISBN
978-1-4244-6685-6
Electronic_ISBN
978-1-4244-6686-3
Type
conf
DOI
10.1109/PACIFICVIS.2010.5429592
Filename
5429592
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