• DocumentCode
    1824432
  • Title

    An automated approach for verification of onchip interconnect resistance for electrostatic discharge paths

  • Author

    Trivedi, N. ; Gossner, H. ; Dhakad, H. ; Stein, B. ; Schneider, J.

  • Author_Institution
    Infineon Technol., Bangalore, India
  • fYear
    2011
  • fDate
    11-16 Sept. 2011
  • Firstpage
    1
  • Lastpage
    8
  • Abstract
    An automated method to verify low-ohmic interconnects for ESD protection network of a multi-million gate SoC design is demonstrated on full chip level. This closes a critical gap in the ESD verification and supersedes workarounds of the past. A structured breakup and assessment of the discharge paths is discussed.
  • Keywords
    electrostatic discharge; integrated circuit design; integrated circuit interconnections; system-on-chip; ESD protection network; electrostatic discharge paths; full chip level; low-ohmic interconnects; multimillion gate SoC design; onchip interconnect resistance verification; Clamps; Discharges; Electrostatic discharge; Equations; Integrated circuit interconnections; Layout; Resistance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2011 33rd
  • Conference_Location
    Anaheim, CA
  • ISSN
    Pending
  • Electronic_ISBN
    Pending
  • Type

    conf

  • Filename
    6045605
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1824432