Title :
Voltage monitor circuit for ESD diagnosis
Author :
Jack, Nathan ; Rosenbaum, Elyse
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
Abstract :
A newly designed on-chip voltage monitor circuit (VM) is capable of recording for subsequent readout the peak voltage reached at internal nodes during ESD events. Real-time voltage probing techniques during wafer-level CDM are verified using VMs; guidelines are discussed for reducing the impact of probing on current flow.
Keywords :
electrostatic discharge; integrated circuit modelling; integrated circuit testing; charged device model; current flow; electrostatic discharge diagnosis; on-chip voltage monitor circuit; realtime voltage probing; wafer-level CDM; Capacitors; Electric potential; Electrostatic discharge; Junctions; Monitoring; Stress; Substrates;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2011 33rd
Conference_Location :
Anaheim, CA
Electronic_ISBN :
Pending
