Multiconfiguration technique to reduce test duration for sequential circuits

Sequential ATPGs, now, are able to handle an appreciable degree of sequentiality, thus allowing to treat partial scan implementations with a suitable fault coverage. Nevertheless, with these methods the test duration remains often prohibitive due to the long scan register. The DFT method we present is based on cycle breaking and sequential depth reduction guided by graph analysis. When a flip-flop is recognized as a pertinent site for breaking cycles, its input line is disconnected. The observability and controllability losses induced by this operation are compensated by the creation of overlapping configurations guided by structural analysis. Results are presented on testability improvement. They illustrate the drastic cycle and sequential depth reduction obtained when passing from an initial circuit to its corresponding configurations. An implementation of the method using scan flip-flops as modified instances is proposed. Comparison with purely scan techniques is presented in terms of fault coverage, test length and number of modified flip-flops