DocumentCode
1825308
Title
A serial scan test vector compression methodology
Author
Su, Chauchin ; Hwang, Kychin
Author_Institution
Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
fYear
1993
fDate
17-21 Oct 1993
Firstpage
981
Lastpage
988
Abstract
This paper presents a serial scan test vector compression methodology for the test time reduction in a scan-based test environment. The reduction is achieved by the overlapping of two consecutive vectors. Hence, the order of test vectors determines the amount of reduction in tiem. Here, two test vector ordering algorithms, depth first greedy and coalesced simple orders algorithms, have been derived, implemented, and tested. Experimental results obtained are very close to estimations by statistical analysis
Keywords
VLSI; boundary scan testing; computational complexity; fault diagnosis; integrated circuit testing; logic testing; statistical analysis; VLSI; iterative methods; overlapping; serial scan test vector compression; statistical analysis; test time reduction; test vector ordering algorithms; Circuit faults; Circuit testing; Compaction; Costs; Design for testability; Digital circuits; Research and development; Sequential analysis; Statistical analysis; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1993. Proceedings., International
Conference_Location
Baltimore, MD
Print_ISBN
0-7803-1430-1
Type
conf
DOI
10.1109/TEST.1993.470601
Filename
470601
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