Title :
On accurate modeling and efficient simulation of CMOS opens
Author :
Di, Chennian ; Jess, J.A.G.
Author_Institution :
Dept. of EE, Eindhoven Univ. of Technol., Netherlands
Abstract :
This paper presents a new modeling and simulation technique for CMOS opens. The significance of the method is that both the hazard and charge-sharing effects of all possible opens are modeled in terms of a set of detecting conditions. They are efficiently represented at logic level. Then during fault simulations only these detecting conditions are evaluated to decide if the opens are detected. In this way, all efficient simulation techniques developed at logic level can be applied. The paper shows how the detecting conditions are derived for arbitrary opens. Results of a parallel pattern simulator show a good trade-off of accuracy versus efficiency
Keywords :
CMOS integrated circuits; circuit analysis computing; digital simulation; fault diagnosis; fault location; integrated circuit modelling; integrated logic circuits; logic testing; parallel processing; CMOS opens; accuracy; accurate modeling; charge-sharing effects; efficiency; efficient simulation; fault simulations; parallel pattern simulator; Bridge circuits; CMOS logic circuits; CMOS technology; Circuit faults; Circuit testing; Computational modeling; Fault detection; Hazards; Semiconductor device modeling; Switches;
Conference_Titel :
Test Conference, 1993. Proceedings., International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-1430-1
DOI :
10.1109/TEST.1993.470613
