Nonlinear copper behavior of TSV for 3D-IC-integration and cracking risks during BEoL-built-up

The application of copper-TSVs for 3D-IC-integration generates novel challenges for reliability analysis and prediction, i.e. to master multiple failure criteria for combined loading including residual stresses, interface delamination, cracking and fatigue. So, the thermal expansion mismatch between copper and silicon yields to stress situation in silicon surrounding the TSVs which is influencing the electron mobility and as a result the transient behavior of transistors. Furthermore, pumping and protrusion of copper is a challenge for Back-end of Line (BEoL) layers of advanced CMOS technologies already during manufacturing. These effects depend highly on the temperature dependent elastic-plastic behavior of TSV-copper and the residual stresses determined by the electro deposition chemistry and annealing conditions.