A synthesis approach to design for testability

We present a new area-efficient procedure for embedding test function into the gate-level implementation of a sequential circuit. We use partition theory and a state variable dependency minimization criterion to map the test function states onto the states of the given circuit. The test generation complexity for our implementation is the same as that for a full scan design. To apply the method to large gate-level designs, we partition the circuit into interconnected finite-state machines. We incorporate test functions into each component machine such that the augmented interconnected machine has the same testability properties as the product machine with test function. Several ISCAS 89 benchmark circuits are partitioned into component finite state machines using a testability-directed partitioned into component finite state machines using a testability-directed partitioning algorithm. Our embedding procedure results in testable circuits that have smaller area than the corresponding full scan designs