Synthesizing for scan dependence in built-in self-testable designs

This paper introduces new design and synthesis techniques that reduce the area and performance overhead of built-in self-test (BIST) architectures such as circular BIST and parallel BIST. Our goal is to arrange the system bistables into scan paths such that some of the BIST and scan logic is shared with the functional logic. Logic sharing is possible when scan dependence is introduced in the design. Other BIST design techniques attempt to avoid scan dependence because it can reduce the fault coverage of embedded, multiple input signature registers (MISRs). We show that introducing certain types of scan dependence in embedded MISRs can result in reduced overhead and improved fault coverage. We present our results for benchmark circuits that have been synthesized to take advantage of scan dependence in a circular BIST architecture