Generation of compact delay tests by multiple path activation

Author

Bose, Soumitra ; Agrawal, Prathima ; Agrawal, Vishwani D.

Author_Institution

AT&T Bell Lab., Murray Hill, NJ, USA

fYear

1993

fDate

17-21 Oct 1993

Firstpage

714

Lastpage

723

Abstract

We use a 23-value logic system to generate robust path delay tests. Each test is successively augmented to detect as many path faults as possible. Other features of the test generator are a podem-like branch and bound search for test, an efficient path designation based on ordering of paths, and an algorithmic selection of secondary target faults for augmenting the tests to cover multiple faults. Results for ISCAS ´89 benchmarks are given

Keywords

automatic test equipment; automatic testing; delays; logic testing; multivalued logic circuits; 23-value logic system; ISCAS ´89 benchmarks; bound search; compact delay tests; efficient path designation; multiple faults; multiple path activation; path faults; podem-like branch; robust path delay tests; secondary target faults; state minimisation; state transition graph; test generator; Algebra; Circuit faults; Circuit testing; Delay; Fault detection; Logic testing; Multivalued logic; Robustness; Sequential circuits; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1993. Proceedings., International

Conference_Location

Baltimore, MD

Print_ISBN

0-7803-1430-1

Type

conf

DOI

10.1109/TEST.1993.470631

Filename

470631

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1826165