An implicit delay fault simulation method with approximate detection threshold calculation

Existing methodologies for determining delay fault coverages or for building up a delay fault dictionary are sometimes accurate, but rarely fast and easy to implement. Therefore, with the aim of removing these deficiencies, a new and more efficient fault simulation strategy for gate delay faults in combinational or scan-based circuits is presented. This method is based on a critical path tracing algorithm, thus avoiding the explicit simulation of each delay fault in the circuit. The novelty of the solution proposed to compute the detection threshold of a detectable delay fault increases the interest of the method, although it is computed approximately. Simulation results obtained for the ISCAS85 combinational benchmark circuits show the efficiency of the proposed method