Title :
Multiple fault diagnosis in printed circuit boards
Author :
Barnfield, S.J. ; Moore, W.R.
Author_Institution :
Dept. of Eng. Sci., Oxford Univ., UK
Abstract :
This paper addresses the problems of diagnosing multiple faults occuring in the non-boundary-scan parts of a printed circuit board. The paper details a diagnostic algorithm based upon combining the fault signatures of single faults in order to produce a pattern which best matches the signature of a multiple fault. In addition, a graphical routine is presented which allows the tester to analyze a given set of test vectors. This analysis provides an implicit fault-simulation process for stuck-at and bridging faults. Furthermore, the process informs the tester of any faults which mask other previously detectable faults within the given test set
Keywords :
automatic testing; fault diagnosis; fault location; logic testing; printed circuit testing; printed circuits; bridging faults; diagnostic algorithm; fault masks; fault signatures; fault-simulation; fuzzy scoring; graphical algorithm; graphical routine; multiple fault; non-boundary-scan parts; printed circuit boards; single faults; stuck at faults; CMOS logic circuits; Circuit faults; Circuit testing; Fault detection; Fault diagnosis; Logic testing; Pattern matching; Printed circuits; Semiconductor device modeling; Voltage;
Conference_Titel :
Test Conference, 1993. Proceedings., International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-1430-1
DOI :
10.1109/TEST.1993.470637
