Low standoff Chip to Wafer bonding

Industry is moving towards having module with multiple functions and capabilities in order to satisfy consumer demands. Miniaturized the package will allowed more components to pack inside the electronic gadget. A low z-foot print of the package is one of the approaches to miniaturize the package. The adoption of micro-bump solders in the chip allowed low standoff Chip to Wafer (C2W) solder interconnects. The chip used in this study is of size 12mm × 12mm × 0.07mm and consists of array of micro-solder bumps at 80μm pitch and 50μm UBM diameter. The wafer is of 200mm diameter and 0.7mm thick. Thermal compression process was adopted to form the solder joint between the chip and wafer. The chip and wafer were subjected to thermal and pressure loading during the thermal compression process. The thermal compression approach ensured that the chip was firmly secured to the wafer before moving to other bonding site on the wafer. This avoids the issue of die shifting during the subsequent bonding process. Several chips can stacked on top of each other as the electrical interconnects can be routed through the use of through silicon vias and double-side Re-route distribution layers (RDL) on the chip. The double RDL fabrication process of the chip involved subjected the micro-bump to several thermal heats. The integrity of the micro-solder bump may be affected by the heat. Thin layer of nickel between the copper bump and solder is necessary to prevent the solder from becoming intermetallic compound before the C2W process. The developed C2W process successfully demonstrated a low standoff micro-bump chip to wafer interconnects.