DocumentCode
1826382
Title
Thin wafer processing - yield enhancement through integrated metrology
Author
Matthias, Thorsten ; Burgstaller, Daniel ; Burggraf, Jürgen ; Kettner, Paul ; Wimplinger, Markus ; Lindner, Paul
Author_Institution
EV Group, St. Florian am Inn, Austria
fYear
2011
fDate
7-9 Dec. 2011
Firstpage
113
Lastpage
116
Abstract
Thin wafer handling and processing is performed by temporary bonding to a rigid carrier wafer. The rigid carrier wafer gives mechanical support during wafer thinning and backside processing. Finally the thin wafer is debonded from the carrier wafer and attached to a dicing tape on film frame. While this technology has been demonstrated for a couple of years now in pilot line and small volume, it is an entirely different story to transfer such a technology to high volume manufacturing (HVM). Yield is the most important consideration for the transfer to HVM. At this point of the manufacturing flow the device wafers have seen complete front end processing and have a significant inherent value. Furthermore, wafer breakage does not only destroy the wafer, but it might be necessary to take the production tool down for chamber cleaning. However, wafer breakage itself is not the only concern. Defects at the wafer edge can nucleate micro cracks in the die, which can result in device failure at a later point of time. In this paper the potential defects during thin wafer processing are reviewed. A new integrated metrology module is presented, which allows 100% in-line inspection with full wafer scanning.
Keywords
inspection; integrated circuit measurement; integrated circuit yield; microcracks; semiconductor device breakdown; semiconductor device manufacture; surface cleaning; wafer bonding; HVM; backside processing; chamber cleaning; dicing tape; film frame; front end processing; full wafer scanning; high volume manufacturing; in-line inspection; integrated metrology module; manufacturing flow; mechanical support; microcracks; production tool; rigid carrier wafer; thin wafer handling; thin wafer processing; wafer breakage; wafer edge defect; wafer thinning; yield enhancement; Bonding; Films; Inspection; Metrology; Performance evaluation; Thermal stability; Through-silicon vias;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Packaging Technology Conference (EPTC), 2011 IEEE 13th
Conference_Location
Singapore
Print_ISBN
978-1-4577-1983-7
Electronic_ISBN
978-1-4577-1981-3
Type
conf
DOI
10.1109/EPTC.2011.6184397
Filename
6184397
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