DocumentCode :
1826427
Title :
Quality testing requires quality thinking
Author :
Soden, Jerry M. ; Hawkins, Charles F.
Author_Institution :
Sandia Nat. Lab., Albuquerque, NM, USA
fYear :
1993
fDate :
17-21 Oct 1993
Firstpage :
596
Abstract :
The stuck-at fault (SAF) model originated from malfunctions in the first types of digital circuits. Many defects in these primitive diode, tube, and bipolar transistor circuits produced symptoms of a node stuck at logic zero or one. Diagnosis of failures was therefore usually based on the assumption of a logically stuck node. As a result, the primary concern for testing at that time was to evaluate the ability of the circuit to perform the intended Boolean function. This history and the compatibility of the SAF model to computer modeling led over the years to the focus on SAF coverage for test pattern generation and grading. It gradually became etched in stone that SAF coverage is an effective and accepted measure of test quality, without supporting defect level data from manufacturers of newer technologies
Keywords :
CMOS logic circuits; automatic testing; fault diagnosis; logic testing; quality control; Boolean function; CMOS IC; SAF coverage; SAF model; computer modeling; defects; digital circuits; logically stuck node; malfunctions; node stuck; stuck at fault model; test pattern generation; Bipolar transistor circuits; Boolean functions; Circuit faults; Circuit testing; Digital circuits; History; Light emitting diodes; Logic circuits; Performance evaluation; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 1993. Proceedings., International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-1430-1
Type :
conf
DOI :
10.1109/TEST.1993.470646
Filename :
470646
Link To Document :
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