Title :
Fault coverage of DC parametric tests for embedded analog amplifiers
Author_Institution :
Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
Abstract :
The test quality of DC parametric manufacturing test sets is evaluated versus the open fault model for analog amplifiers. Using two case studies in CMOS and bipolar technologies, the fault coverage of the test set is shown to be rather low (less than 80%). Several open faults in the signal path remain undetected. When the amplifiers are embedded in a larger circuit, the functional test set is usually unable to detect these faults as well. Detection is strongly correlated to circuit topology in two signal processing circuits used as examples. Test selection guidelines are presented to improve the fault coverage. Circuit redundancies are identified as the fundamental factor affecting test quality, and a method to recognize redundancy using the open fault model is proposed
Keywords :
CMOS analogue integrated circuits; bipolar analogue integrated circuits; fault diagnosis; fault location; network topology; operational amplifiers; CMOS; DC parametric tests; analog amplifiers; circuit redundancy; circuit topology; embedded analog amplifiers; fault coverage; functional test set; manufacturing test sets; open fault model; redundancy; signal processing circuits; CMOS technology; Circuit faults; Circuit testing; Circuit topology; Electrical fault detection; Fault detection; Redundancy; Semiconductor device modeling; Signal processing; Virtual manufacturing;
Conference_Titel :
Test Conference, 1993. Proceedings., International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-1430-1
DOI :
10.1109/TEST.1993.470653
