Digit-serial implementation of LDI/LDD allpass filters

Author

Landernäs, Krister ; Holmberg, Johnny ; Harnefors, Lennart ; Vesterbacka, Mark

Author_Institution

Dept. of Electron., Malardalen Univ., Vasteras, Sweden

Volume

2

fYear

2002

fDate

2002

Abstract

In this paper we study digit-serial implementation of the general-order lossless discrete integrator/differentiator (LDI/LDD) allpass filter structure. In low-power filter implementation, digit-serial computation has been shown to be advantageous compared to bit-serial and parallel arithmetics. The digit-serial processing elements are obtained using unfolding techniques. The implementation is compared to a corresponding wave digital (WD) implementation. It is shown in an example that a WD realization requires about 60% and 30% more D flip-flops for pipelining and shimming delays, respectively, than the corresponding LDI/LDD implementation. We also study the sample period of the second-order LDI/LDD allpass filter using different digit sizes and conclude that when the filter is scheduled over a number of sample periods we achieve the shortest sample period

Keywords

all-pass filters; differentiating circuits; digital filters; integrating circuits; low-power electronics; pipeline processing; D flip-flop; LDI/LDD all-pass filter; digit-serial processing; lossless discrete integrator/lossless discrete differentiator all-pass filter; low-power filter; pipelining delay; shimming delay; single interval scheduling; unfolding technique; wave digital filter; Arithmetic; Chebyshev approximation; Concurrent computing; Delay; Digital filters; Flip-flops; Frequency; Lattices; Passband; Pipeline processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Conference_Location

Phoenix-Scottsdale, AZ

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1011445

Filename

1011445