DocumentCode
1826677
Title
Timing analyzer for embedded testing
Author
Frisch, Arnold ; Almy, Thomas
Author_Institution
Tektronix, Inc., Beaverton, OR, USA
fYear
1993
fDate
17-21 Oct 1993
Firstpage
552
Lastpage
555
Abstract
A 20 channel timing analyzer was designed in CMOS for embedded testing applications. The chip executes independent events in each of the channels at rates of 100 MHz, with a precision of 312.5 ps. The chip automatically adjusts for clock rates from 10 to 100 MHz and temperature/process variations, and can be calibrated to compensate for clock skew
Keywords
CMOS integrated circuits; automatic test equipment; multichip modules; printed circuit testing; 10 to 100 MHz; 100 MHz; 312.5 ps; CMOS; calibration; clock rates; clock skew; embedded testing; three state transceiver; timing analyser; timing analyzer; timing interpolator; Circuit analysis; Circuit testing; Clocks; Delay; Independent component analysis; Inverters; Logic; Printed circuits; Timing; Transceivers;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1993. Proceedings., International
Conference_Location
Baltimore, MD
Print_ISBN
0-7803-1430-1
Type
conf
DOI
10.1109/TEST.1993.470655
Filename
470655
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