Partial scan using reverse direction empirical testability

The empirical testability difference (ETD) method for selecting flip-flops (FFs) achieved results superior to compared methods at the expense of substantial CPU time. The new reverse empirical testability difference (RETD) approach starts from a fully scanned circuit and, through several iterations, drops these FFs from the scan chain that have the least effect on the overall circuit testability. In order to further enhance processing efficiency. relative sequential observability, a new distance measure between FFs, permits multiple FFs to be dropped from the scan chain in a single iteration. RETD maintains the same desirable fault coverage-hardware overhead characteristics as ETD. We compare RETD results for a subset of ISCAS89 circuits with a cycle breaking and depth reduction-based method. The results indicate that RETD, in general, achieves better fault coverage for given hardware overhead. The overall amount of CPU time required to achieve comparable, fault-coverage targeted solutions is also shorter for RETD