Title :
Sum-of-products computation based on a weight-sorting algorithm
Author :
Choi, Jae Hun ; Swartzlander, Earl E., Jr.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
An architecture for sum-of-products computation using conventional carry-save-adder arrays including even/odd CSA array is regular, however, it results in awkward inter-layer interconnections and elongated interconnection length. We introduce a "weight-sorting" CSA array which minimizes the interconnection complexity. This array can be designed in a systematic way and laid out regularly in a VLSI circuit using narrow cells. A comparison is made between three CSA arrays at an architectural level. The design of a 8/spl times/8 sum-of-two-products computer using the weight-sorting algorithm and the narrow cells is studied as an illustration.
Keywords :
VLSI; adders; carry logic; digital arithmetic; integrated circuit interconnections; integrated circuit layout; parallel algorithms; parallel architectures; VLSI circuit; architecture; carry-save-adder arrays; floor plan; interconnection complexity minimization; regular even/odd CSA array; sum-of-products computation; sum-of-two-products computer; weight-sorting CSA array; weight-sorting algorithm; Adders; Algorithm design and analysis; Arithmetic; Computer architecture; Integrated circuit interconnections; Military computing; Propagation delay; Signal design; Sorting; Very large scale integration;
Conference_Titel :
Signals, Systems, and Computers, 1999. Conference Record of the Thirty-Third Asilomar Conference on
Conference_Location :
Pacific Grove, CA, USA
Print_ISBN :
0-7803-5700-0
DOI :
10.1109/ACSSC.1999.831930
