Partial scan at the register-transfer level

This paper presents a partial scan methodology suited for (pipelined) data paths described at the register-transfer level. The method is based on feedback elimination by making existing registers scanable or by adding extra transparent scan registers. An optimal set (in terms of area cost) of scan registers is selected using an exact branch and bound algorithm. Our symbolic test pattern generation technique can very effectively deal with the delay in the remaining sequential circuit parts. Furthermore, the symbolic test method makes various scan schemes possible which ensures a correct application and evaluation of the test vectors. They are discussed and compared in terms of their hardware requirements, test application times and test accuracy