Title :
Performance limitations of block-multithreaded distributed-memory systems
Author_Institution :
Dept. of Comput. Sci., Memorial Univ., St. John´´s, NL, Canada
Abstract :
The performance of modern computer systems is increasingly often limited by long latencies of accesses to the memory subsystems. Instruction-level multithreading is an architectural approach to tolerating such long latencies by switching instruction threads rather than waiting for the completion of memory operations. The paper studies performance limitations in distributed-memory block multithreaded systems and determines conditions for such systems to be balanced. Event-driven simulation of a timed Petri net model of a simple distributed-memory system confirms the derived performance results.
Keywords :
Petri nets; discrete event simulation; distributed memory systems; multi-threading; block-multithreaded distributed-memory systems; computer systems; event-driven simulation; instruction-level multithreading; switching instruction thread; timed Petri net model; Cache memory; Computational modeling; Computer science; Computer simulation; Delay; Discrete event simulation; Distributed computing; Manufacturing processes; Multithreading; Yarn;
Conference_Titel :
Simulation Conference (WSC), Proceedings of the 2009 Winter
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-5770-0
DOI :
10.1109/WSC.2009.5429718
