Minimizing test time by exploiting parallelism in macro test

Increasing complexity of modern designs and high costs of test equipment are putting more and more emphasis on test application times. This paper presents a classification of methods for reducing the test time of a device by exploiting parallelism in Macro Test. Techniques and considerations are given for different methods of parallel testing. It is shown that without design modifications significant reductions in test time can be reached. To obtain a further test time reduction, analysis of resource sharing conflicts is done in order to be able to decide which design modifications can best be made. As a result, a trade-off between test time and additional testability hardware can be made. Results of one of the methods of parallel testing are given for two industrial devices. Test time reductions of up to 40-50% compared to sequential approaches have been reached without making any design modifications