Distributed implementation of an ATPG system using dynamic fault allocation

This paper presents a new approach to a distributed ATPG system for large combinational circuits. Although several ATPG parallel implementations have been developed, many of them rely on the use of very specialized and expensive hardware. However, the proposed implementation is built over an heterogeneous network of workstations, which is normally available at all design labs. The proposed parallelization scheme is based on an integrated random and deterministic test vector generation/fault simulation environment, combined with an efficient fault list partitioning strategy and a dynamic communication structure. Reduced numbers of test vectors and significant speed-up factors are reported