Trade-offs in designing a VHDL simulation tool for digital VLSI

The authors present an original logical simulation tool called ASIMUT and discusses the considerations that have driven the design of this tool. ASIMUT uses a VHDL description. It is freely distributed through the ALLIANCE CAD System (a complete CAD system for digital VLSI design). First, they present the VHDL subset supported by the compiler and, the way this subset has been defined. In a second part, the internal architecture of the tool is detailed. Unlike, most simulators available on the market which use a compiled-code method, they have chosen to represent the source code by the means of data structures. The event-driven algorithm implemented in the simulator runs directly on these data structures. Logical expressions are represented by Binary Decision Diagram. The paper concludes with results showing the performance of the simulator on some benchmarks and life-size examples